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Intel MAX 10 FPGA Device Datasheet

This datasheet describes the electrical characteristics, switching characteristics, configuration specifications, and timing for Intel® MAX® 10 devices.

Device gradeSpeed ​​Grade Supported
Commercial
Industrial
Automotive
Note: The -I6 and -A6 speed grades of the Intel® MAX® 10 FPGA devices are not available by default in the Intel® Quartus® Prime software. Contact your local Intel sales representatives for support.

The following sections describe the operating conditions and power consumption of Intel® MAX® 10 devices.

Intel® MAX® 10 devices are rated according to a set of defined parameters. To maintain the highest possible performance and reliability of the Intel® MAX® 10 devices, you must consider the operating requirements described in this section.

This section defines the maximum operating conditions for Intel® MAX® 10 devices. The values ​​are based on experiments conducted with the devices and theoretical modeling of breakdown and damage mechanism. The functional operation of the device is not implied for these conditions.

Conditions outside the range listed in the absolute maximum ratings tables may cause permanent damage to the device. Additionally, device operation at the absolute maximum ratings for extended periods of time may have adverse effects on the device.
symbolparameterMinMaxUnit
V.CC_ONESupply voltage for core and periphery through on-die voltage regulator –0.53.9V.
V.CCIOSupply voltage for input and output buffers–0.53.9V.
V.CCASupply voltage for phase-locked loop (PLL) regulator and analog-to-digital converter (ADC) block (analog)–0.53.9V.
symbolparameterMinMaxUnit
V.CCSupply voltage for core and periphery–0.51.63V.
V.CCIOSupply voltage for input and output buffers–0.53.9V.
V.CCASupply voltage for PLL regulator (analog)–0.53.41V.
V.CCD_PLLSupply voltage for PLL regulator (digital)–0.51.63V.
V.CCA_ADCSupply voltage for ADC analog block–0.53.41V.
V.CCINTSupply voltage for ADC digital block–0.51.63V.
symbolparameterMinMaxUnit
V.I.DC input voltage–0.54.12V.
I.OUTDC output current per pin–2525mA
TSTGStorage temperature–65150° C
TJOperating junction temperature–40125° C

During transitions, input signals may overshoot to the voltage listed in the following table and undershoot to –2.0 V for input currents less than 100 mA and periods shorter than 20 ns.

The maximum allowed overshoot duration is specified as a percentage of high time over the lifetime of the device. A DC signal is equivalent to 100% duty cycle.

For example, a signal that overshoots to 4.17 V can only be at 4.17 V for ~ 11.7% over the lifetime of the device; for a device lifetime of 11.4 years, these amounts to 1.33 years.

Condition (V)Overshoot Duration as% of High TimeUnit
4.12100.0%
4.1711.7%
4.227.1%
4.274.3%
4.322.6%
4.371.6%
4.421.0%
4.470.6%
4.520.3%
4.570.2%

This section lists the functional operation limits for the AC and DC parameters for Intel® MAX® 10 devices.The tables list the steady-state voltage values ​​expected from Intel® MAX® 10 devices. Powersupply ramps must all be strictly monotonic, without plateaus.

symbolparameterConditionMinTypeMaxUnit
V.CC_ONE1Supply voltage for core and periphery through on-die voltage regulator 2.85/3.1353.0/3.33.15/3.465V.
V.CCIO2Supply voltage for input and output buffers3.3 V3.1353.33.465V.
3.0 V2.8533.15V.
2.5 V2.3752.52.625V.
1.8 V1.711.81.89V.
1.5 V1.4251.51.575V.
1.35 V1.28251.351.4175V.
1.2 V1.141.21.26V.
1.0 V0.951.01.05V.
V.CCA1Supply voltage for PLL regulator and ADC block (analog)2.85/3.1353.0/3.33.15/3.465V.
1 V.CCA must be connected to VCC_ONE through a filter.
2 V.CCIO for all I / O banks must be powered up during user mode because VCCIO I / O banks are used for the ADC and I / O functionalities.
symbolparameterConditionMinTypeMaxUnit
V.CCSupply voltage for core and periphery1.151.21.25V.
V.CCIO3Supply voltage for input and output buffers3.3 V3.1353.33.465V.
3.0 V2.8533.15V.
2.5 V2.3752.52.625V.
1.8 V1.711.81.89V.
1.5 V1.4251.51.575V.
1.35 V1.28251.351.4175V.
1.2 V1.141.21.26V.
1.0 V0.951.01.05V.
V.CCA4Supply voltage for PLL regulator (analog)2.3752.52.625V.
V.CCD_PLL5Supply voltage for PLL regulator (digital)1.151.21.25V.
V.CCA_ADCSupply voltage for ADC analog block2.3752.52.625V.
V.CCINTSupply voltage for ADC digital block1.151.21.25V.
3 V.CCIO for all I / O banks must be powered up during user mode because VCCIO I / O banks are used for the ADC and I / O functionalities.
4 All VCCA pins must be powered to 2.5 V (even when PLLs are not used), and must be powered up and powered down at the same time.
5 V.CCD_PLL must always be connected to VCC through a decoupling capacitor and ferrite bead.
symbolparameterConditionMinMaxUnit
V.I.DC input voltage–0.53.6V.
V.OOutput voltage for I / O pins0V.CCIOV.
TJOperating junction temperatureCommercial085° C
Industrial–40 6100° C
Automotive–406125° C
tRAMPPower supply ramp time710ms
I.diodeMagnitude of DC current across PCI * clamp diode when enabled10mA
6 -40 ° C is only applicable to the start of the test when the device is powered-on. The device does not stay at the minimum junction temperature for a long time.
7 There is no absolute minimum value for the ramp time requirement. Intel characterized the minimum ramp time at 200 μs.
Erase and reprogram cycles (E / P) 8 (Cycles / page)Temperature (° C)Data retention duration (years)
10,0008520
10,00010010
8 The number of E / P cycles applies to the smallest possible flash block that can be erased or programmed in each Intel® MAX® 10 device. Each Intel® MAX® 10 device has multiple flash pages per device.

Intel offers two ways to estimate power for your design — the Excel-based Early Power Estimator (EPE) and the Intel® Quartus® Prime Power Analyzer feature.

Use the Excel-based EPE before you start your design to estimate the supply current for your design. The EPE provides a magnitude estimate of the device power because these currents vary greatly with the usage of the resources.

The Intel® Quartus® Prime Power Analyzer provides better quality estimates based on the specifics of the design after you complete place-and-route. The Power Analyzer can apply a combination of user-entered, simulation-derived, and estimated signal activities that, when combined with detailed circuit models, yield very accurate power estimates.

The values ​​in the table are specified for normal device operation. The values ​​vary during device power-up. This applies for all VCCIO settings (3.3, 3.0, 2.5, 1.8, 1.5, 1.35, and 1.2 V).

10 µA I / O leakage current limit is applicable when the internal clamping diode is off. A higher current can be observed when the diode is on.

Input channel leakage of ADC I / O pins due to hot socket is up to maximum of 1.8 mA. The input channel leakage occurs when the ADC IP core is enabled or disabled. This is applicable to all Intel® MAX® 10 devices with ADC IP core, which are 10M04, 10M08, 10M16, 10M25, 10M40, and 10M50 devices. The ADC I / O pins are in Bank 1A.

symbolparameterConditionMinMaxUnit
I.I.Input pin leakage currentV.I. = 0 V to VCCIOMAX–1010µA
I.OZTristated I / O pin leakage currentV.O = 0 V to VCCIOMAX–1010µA
symbolparameterConditionMinMaxUnit
I.adc_vref pin leakage currentSingle supply mode10µA
Dual supply mode20µA

Bus hold retains the last valid logic state after the source driving it either enters the high impedance state or is removed. Each I / O pin has an option to enable bus hold in user mode. Bus hold is always disabled in configuration mode.

parameterConditionV.CCIO (V)Unit
1.21.51.82.53.03.3
MinMaxMinMaxMinMaxMinMaxMinMaxMinMax
Bus hold low, sustaining currentV.IN > VIL (maximum)81230507070µA
Bus-hold high, sustaining currentV.IN IH (minimum)–8–12–30–50–70–70µA
Bus hold low, overdrive current0 V IN CCIO125175200300500500µA
Bus hold high, overdrive current0 V IN CCIO–125–175–200–300–500–500